|Dr. Un-Byoung Kang, Master
Samsung Electronics Co., Ltd., Korea
“Advanced Packaging Solution for Heterogeneous Integration – Status and Challenges”
Currently higher computing power, high capacity and performance of memory are the major requirements of Al and GPU, accelerators and network devices. These demands lead to the adoption of the advanced packaging technologies to increase bandwidth density, thermal performance and to improve electrical performance with shorter interconnection length. High-performance chip size continues to increase up over one reticle size and the cost of the leading-edge silicon node is recently soaring. So various chiplet packaging solutions, such as 2D, 2.5D and 3D have been introduced. Among these solutions, the highest density and speed can be obtained with 3D IC packaging technology. Stacked 3D ICs contain multiple dies stacked, aligned, and bonded in a single package, using through-silicon vias (TSVs) and hybrid bonding techniques for inter-die communication. In this presentation, the above mentioned advanced package solutions are to be introduced as well as the status and challenges in terms of process development in stacked 3D IC packaging.
Un-Byoung Kang received the Ph.D. degree in material science and engineering from the Hanyang University, Seoul, South Korea, in 2004. He joined Samsung Electronics, Kiheung, South Korea, in 2004, where he was involved in the semiconductor packaging process development like bumping, Cu RDL, TSV via last, wafer supporting system, and 3D chip bonding as well as the package product development such as WLP, CIS-CSP, 3D TSV-SIP, EDP-TSV, and HBM. He is currently a Master (VP of Technology) in advanced packaging process development team.
|Dr. Jiho Kang, Fellow
SK Hynix Inc., Korea
“An Overview of the Past, Present and Future of 3D Device Technology”
In 1965, Moore’s Law, which states that the number of transistors in an integrated silicon circuit doubles about every two years, has been slowed due to the limitation of the interconnect pitch scaling. Therefore, many IDM companies are currently focusing on the development of micro-processes that reduce the chip size by developing new process integration such as multilayer or 3D structure device technology. However, due to the large process cost of the FEOL process development to achieve the above-described goals, significant efforts are being made to open the era of “Beyond the Moore” with the development of backend & package process technology. In this presentation, the past, present and future of 3D stacking technology that can respond to the 4th industrial revolution era and overcome structural limitations for semiconductor integration will be discussed.
Dr. Jiho Kang is the Fellow in the R&D Division of SK Hynix, Korea and currently leading WF Bonding PJT in the R&D Process.
Dr. Kang first joined Intel Corporation in Hillsboro, Oregon in 2006 and worked as a senior etch process engineer. From 2012, he participated in the development of Intel TSV process technology, which became the basis of Intel FoverosTM Technology. From 2016, he worked as a group leader, responsible for BEOL process development for Intel 14, 10 & 7nm technology nodes.
Dr. Kang received Ph.D. in Materials Science and Engineering from The Ohio State University, Columbus, Ohio. Previously, he earned B.S. in the Metallurgical Engineering from Yonsei University and M.S. degree in Materials Science and Engineering from KAIST in Korea.
|Sir. Jim Cao, Senior VP
Universal Scientific Industrial Co., Ltd. (USI) *ASE Group, China
“SiP, The Next Revolution for Microelectronics Packaging and The Challenges”
The entire microelectronics packaging industry has been driven by consumer market harder and harder over the last 10 years for providing smaller footprint and thinner product solutions. Now the entire industry is approaching the critical barrier breaking point to continue the miniaturization trend for the next 10 years and the only major solution to the challenge is SiP packaging technology. In this presentation, some of the major SiP manufacturing technical challenges and solutions will be discussed to provide value add reference for our audience.
Jing (Jim) Cao is Sr. Vice President, General Manager of USI Asia I Region & SiM Business Unit.
Jim leads USI’s largest operation group that provides engineering development and manufacturing service of the largest SiP (System in Package) product volume in the world.
Since joining Motorola Semiconductor in 1993, Jim has spent almost his entire career in semiconductor new product development and manufacturing operations. Before joining USI in April, 2015, Jim was the Sr. Vice President of Operations for UTAC where he led five semiconductor manufacturing sites in Asia. Prior to UTAC, Jim was the Vice President of Engineering, Chief Manufacturing Engineer at TE Connectivity where he led worldwide manufacturing engineering teams to improve manufacturing processes and gross margin. After joining Vitesse Semiconductor in 2001 Jim advanced his career to Vice President Operations and Technology, Vice President of Operations, and Sr. Vice President of Operations at Vitesse Semiconductor, Hoya/Xponent, and Mindspeed Technologies where he led worldwide operations team to achieve significant operating performance improvement and market cap increase.
Jim holds a Master of Science degree in Mechanical Engineering and a Master of Engineering degree in Industrial Engineering from Arizona State University, USA.
|Prof. Sung Kyu Lim
Georgia Institute of Technology, Program Manager/ DARPA, USA
“Glass Interposer Integration of Logic and Memory Chiplets: PPA and Reliability Benefits”
Glass interposer offers low-cost options to embed chiplets directly inside the substrate itself. This enables 3D stacking configuration between the embedded dies and the conventional flip-chip dies mounted directly on top. Furthermore, the interconnect pitch and through-glass-via (TGV) diameter in glass are becoming comparable to their counterparts in silicon. In this work, we investigate the power, performance, area (PPA), signal integrity (SI), and power integrity (PI) benefits of 3D stacking enabled by glass interposer in comparison with silicon interposer. Our research is based on chiplet/package co-design, where our design start is a register transfer level (RTL) description of RISC-V architecture for the chiplets. Our final design reaches graphic data system (GDS) layouts of the chiplets and their routing in interposers. Our experiments show that the 3D glass design is 2.58X smaller than the 2.5D, and 1.36X smaller than the 2D design. Our glass interposer shows 20.8X shorter wirelength, 10X smaller PDN DC impedance, and 9.7% faster settling time for switching voltage compared with silicon. Lastly, the eye opening in glass is 15% larger than silicon.
Prof. Sung Kyu Lim received Ph.D. degree from UCLA in 2000. He joined the School of Electrical and Computer Engineering at the Georgia Institute of Technology in 2001, where he is currently Motorola Solutions Foundation Professor. His research focus is on the architecture, design, and electronic design automation for 2.5D and 3D ICs. He has published more than 400 papers on the topics. He received the Best Paper Award from the IEEE Transactions on Electromagnetic Compatibility in 2021 and the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems in 2022. He began serving as a program manager for DARPA Microsystems Technology Office (MTO) since 2022.